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cy62146ev30 mobl ? 4-mbit (256 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05567 rev. *j revised april 16, 2014 4-mbit (256 k 16) static ram features very high speed: 45 ns temperature ranges ? industrial: ?40 c to +85 c ? automotive-a: ?40 c to +85 c wide voltage range: 2.20 v to 3.60 v pin compatible with cy62146dv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in a pb-free 48-ball very fine ball grid array (vfbga) and 44-pin tsop ii packages functional description the cy62146ev30 is a high performance cmos static ram organized as 256k words by 16 bits. this device features an advanced circuit design designed to provide an ultra low active current. ultra low active current is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly r educes power consumption by 80 percent when addresses are not t oggling.the device can also be put into standby mode reducing power consumption by more than 99 percent when deselected (ce high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or a write operation is in progress (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from the i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. logic block diagram 256k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we bhe a 16 a 0 a 1 a 9 a 10 ble a 17
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 2 of 18 contents pin configurations ........................................................... 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagrams .......................................................... 13 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 18 worldwide sales and design s upport ......... .............. 18 products .................................................................... 18 psoc? solutions ...................................................... 18 cypress developer community ................................. 18 technical support ................. .................................... 18
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 3 of 18 pin configurations figure 1. 48-ball vfbga pinout [1, 2] figure 2. 44-pin tsop ii pinout [1] we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe nc a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss a 17 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 15 a 16 a 8 a 9 a 10 a 11 a 13 a 14 a 12 oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 a 17 product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max cy62146ev30ll industrial / automotive-a 2.2 3.0 3.6 45 2 2.5 15 20 1 7 notes 1. nc pins are not connected on the die. 2. pins h1, g2, and h6 in the bga package are address expansion pins for 8 mb, 16 mb and 32 mb, respectively. 3. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 4 of 18 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............................... ?65 c to + 150 c ambient temperature with power applied ......................................... ?55 c to + 125 c supply voltage to ground potential .......................... ?0.3 v to + 3.9 v (v ccmax + 0.3 v) dc voltage applied to outputs in high-z state [4, 5] ............ ?0.3 v to 3.9 v (v ccmax + 0.3 v) dc input voltage [4, 5] ....... ?0.3 v to 3.9 v (v cc max + 0.3 v) output current into outputs (low) ............................. 20 ma static discharge voltage (per mil-std-883, method 3015) .......................... >2001 v latch-up current .................................................... >200 ma operating range device range ambient temperature v cc [6] cy62146ev30 industrial / automotive-a ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 45 ns (ind?l/auto-a) unit min typ [7] max v oh output high voltage i oh = ?0.1 ma 2.0 ? ? v i oh = ?1.0 ma, v cc > 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.4 v i ol = 2.1 ma, v cc > 2.70 v ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3 v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3 v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) , i out = 0 ma cmos levels ?1520ma f = 1 mhz ? 2 2.5 i sb1 automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = 3.60 v ?17 ? a i sb2 [8] automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?17 ? a notes 4. v il(min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a minimum of 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 8. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 5 of 18 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions vfbga tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 75 77 ? c/w ? jc thermal resistance (junction to case) 10 13 ? c/w ac test loads and waveforms figure 3. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v all input pulses r th r1 equivalent to: thevenin equivalent parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v note 9. tested initially and after any design or proces s changes that may affect these parameters.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 6 of 18 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.5 ? ? v i ccdr [11] data retention current v cc = 1.5 v, ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v industrial / automotive-a ?0.87 ? a t cdr [12] chip deselect to data retention time ? 0??ns t r [13] operation recovery time ? 45 ? ? ns data retention waveform figure 4. data retention waveform v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce notes 10. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enable (ce) and byte enables (bhe and ble) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. 12. tested initially and after any design or process changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 7 of 18 switching characteristics over the operating range parameter [14, 15] description 45 ns (industrial / automotive-a) unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low-z [16] 5 ? ns t hzoe oe high to high-z [16, 17] ? 18 ns t lzce ce low to low-z [16] 10 ? ns t hzce ce high to high-z [16, 17] ? 18 ns t pu ce low to power up 0 ? ns t pd ce high to power down ? 45 ns t dbe ble / bhe low to data valid ? 22 ns t lzbe ble / bhe low to low-z [16] 5 ? ns t hzbe ble / bhe high to high-z [16, 17] ? 18 ns write cycle [18, 19] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble / bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high-z [16, 17] ? 18 ns t lzwe we high to low-z [16] 10 ? ns notes 14. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 v/ns) or less, t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 3 on page 5 . 15. in an earlier revision of this device, under a specific applic ation condition, read and write operations were limited to swi tching of the byte enable and/or chip enable signals as described in the application notes an13842 and an66311 . however, the issue has been fixed and in production now, and hence, these application notes are no longer applicable. they are av ailable for download on our website as they contain information on the date code of the parts, beyond which the fix has been in production. 16. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 17. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedance state. 18. the internal write time of the memo ry is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data in put setup and hold timing must be referenced to the edge of t he signal that terminates the write 19. the minimum write pulse width for write cycle no. 3 (we controlled, oe low) should be sum of t hzwe and t sd .
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 8 of 18 switching waveforms figure 5. read cycle 1 (address transition controlled) [20, 21] figure 6. read cycle no. 2 (oe controlled) [21, 22] previous data valid data out valid t rc t aa t oha address data i/o 50% 50% data out valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data i/o oe ce v cc supply current bhe /ble address notes 20. the device is continuously selected. oe , ce = v il , bhe and/or ble = v il . 21. we is high for read cycle. 22. address valid before or similar to ce and bhe , ble transition low.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 9 of 18 figure 7. write cycle no. 1 (we controlled) [23, 24, 25] figure 8. write cycle no. 2 (ce controlled) [23, 24, 25] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 26 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 26 notes 23. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input se tup and hold timing must be referenced to the edge of the sig nal that terminates the write. 24. data i/o is high impedance if oe = v ih . 25. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 26. during this period, the i/os are in output state and input signals must not be applied.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 10 of 18 figure 9. write cycle no. 3 (we controlled, oe low) [27, 28] figure 10. write cycle no. 4 (bhe /ble controlled, oe low) [27] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 29 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 29 data i/o address ce we bhe /ble notes 27. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 28. the minimum write pulse width for write cycle no. 3 (we controlled, oe low) should be sum of t hzwe and t sd . 29. during this period, the i/os are in output state and input signals must not be applied.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 11 of 18 truth table ce [30] we oe bhe ble inputs/outputs mode power h x x x x high-z deselect/power-down standby (i sb ) l x x h h high-z output disabled active (i cc ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) l h l h l data out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high-z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high-z read active (i cc ) l h h l l high-z output disabled active (i cc ) l h h h l high-z output disabled active (i cc ) l h h l h high-z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high-z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high-z write active (i cc ) note 30. chip enable must be at cmos levels (not floating). in termediate voltage levels on this pin is not permitted.
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 12 of 18 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 45 cy62146ev30ll-45bvxi 51-85150 48-ball vfbga (pb-free) industrial cy62146ev30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) cy62146ev30ll-45zsxa 51-85087 44-pin ts op ii (pb-free) automotive-a please contact your local cypress sales repr esentative for availability of other parts temperature grade: x = i or a i = industrial; a = automotive pb-free package type: xx = bv or zs bv = vfbga; zs = tsop ii speed grade: 45 ns ll = low power voltage range: v30 = 3 v typical process technology: e = 90 nm buswidth: 6 = 16 density: 4 = 4-mbit family code: mobl sram family company id: cy = cypress cy 45 xx 621 4 6 e v30 ll x x -
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 13 of 18 package diagrams figure 11. 48-ball vfbga (6 8 1.0 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 14 of 18 figure 12. 44-pin tsop z4 4-ii package outline, 51-85087 package diagrams (continued) 51-85087 *e
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 15 of 18 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory tsop thin small outline package vfbga very fine-pitch ball gird array we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ma milliampere ns nanosecond ? ohm pf picofarad v volt w watt
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 16 of 18 document history page document title: cy62146ev30 mobl ? , 4-mbit (256 k 16) static ram document number: 38-05567 rev. ecn no. orig. of change submission date description of change ** 223225 aju see ecn new data sheet. *a 247373 syt see ecn changed status from advance information to preliminary. moved product portfolio to page 2 changed v cc stabilization time in footnote #8 from 100 ? s to 200 ? s removed footnote #14(t lzbe ) from previous revision changed i ccdr from 2.0 ? a to 2.5 ? a changed typo in data retention characteristics (t r ) from 100 ? s to t rc ns changed t oha from 6 ns to 10 ns for both 35 ns and 45 ns speed bin changed t hzoe , t hzbe , t hzwe from 12 to 15 ns for 35 ns speed bin and 15 to 18 ns for 45 ns speed bin changed t sce and t bw from 25 to 30 ns for 35 ns speed bin and 40 to 35 ns for 45 ns speed bin changed t hzce from 12 to 18 ns for 35 ns speed bin and 15 to 22 ns for 45 ns speed bin changed t sd from 15 to 18 ns for 35 ns speed bin and 20 to 22 ns for 45 ns speed bin changed t doe from 15 to 18 ns for 35 ns speed bin changed t dbe from 15 to 18 ns for 35 ns speed bin changed ordering information to include pb-free packages *b 414807 zsd see ecn changed from preliminary information to final changed the address of cypress semiconductor corporation on page #1 from ?3901 north first street? to ?198 champion court? removed 35ns speed bin removed ?l? version of cy62146ev30 changed ball e3 from dnu to nc removed the redundant foot note on dnu. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f=1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max changed i sb1 and i sb2 typ values from 0.7 ? a to 1 ? a and max values from 2.5 ? a to 7 ? a. changed the ac test load capacitance from 50pf to 30pf on page# 4 changed i ccdr from 2.5 ? a to 7 ? a. added i ccdr typical value. changed t lzoe from 3 ns to 5 ns changed t lzce and t lzwe from 6 ns to 10 ns changed t lzbe from 6 ns to 5 ns changed t hzce from 22 ns to 18 ns changed t pwe from 30 ns to 35 ns. changed t sd from 22 ns to 25 ns. updated the package diagram 48-ball vfbga from *b to *d updated the ordering information table and replaced the package name column with package diagram. *c 925501 vkn see ecn added footnote #8 related to i sb2 and i ccdr added footnote #12 related ac timing parameters *d 2678796 vkn / pyrs 03/25/2009 added automotive-a information *e 2944332 vkn 06/04/2010 added contents removed byte enable from footnote #2 in electrical characteristics added footnote related to chip enable in truth table updated package diagrams updated links in sales, solutions, and legal information
cy62146ev30 mobl ? document number: 38-05567 rev. *j page 17 of 18 *f 3109050 pras 12/13/2010 changed ta ble footnotes to footnotes. added ordering code definitions. *g 3302915 rame 07/14/2011 rem oved the references of an1064 sr am system guide lines from the datasheet. updated all the notes. ordering code definition updated. added units of measure table. updated as per template. *h 3961126 tava 04/10/2013 updated package diagrams : spec 51-85150 ? changed revision from *f to *h. spec 51-85087 ? changed revision from *c to *e. completing sunset review. *i 4101995 vini 08/22/2013 updated switching characteristics : updated note 15. updated in new template. *j 4348752 memj 04/16/2014 updated switching characteristics : added note 19 and referred the same note in ?write cycle? (for t pwe parameter in we controlled, oe low write cycle). updated switching waveforms : added note 28 and referred the same note in figure 9 (for t pwe parameter in we controlled, oe low write cycle). completing sunset review. document history page (continued) document title: cy62146ev30 mobl ? , 4-mbit (256 k 16) static ram document number: 38-05567 rev. ecn no. orig. of change submission date description of change
document number: 38-05567 rev. *j revised april 16, 2014 page 18 of 18 mobl is a registered trademark, and more battery life is a trademark of cypress semiconductor. all product and company names me ntioned in this document are the tr ademarks of their respective holders. cy62146ev30 mobl ? ? cypress semiconductor corporation, 2004-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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